Nonvolatile memories such as an Electrically Programmable Read Only Memory ("EPROM"), Electrically Erasable Programmable Read Only Memory ("EEPROM"), and flash EEPROM use a variety of memory cell designs. One type of nonvolatile memory cell uses an electrically isolated floating gate to trap charge. A variety of mechanisms can be used to program or trap charge on the floating gate, including hot electron injection and Fowler-Nordheim tunneling. Each program technique must provide appropriate voltages to the terminals of the nonvolatile memory cell in order to accurately program the desired amount of charge on the floating gate.
FIG. 1 shows a nonvolatile memory circuit 100 that includes a nonvolatile memory cell 118 coupled to a load line circuit 112. The nonvolatile memory cell can be programmed by applying a gate voltage VG of approximately 12 volts, a drain voltage VD of approximately 7 -9 volts, and connecting the source terminal to ground. It is important to achieve and maintain these voltage ranges during programming of nonvolatile memory cell 118.
A programming voltage VD is applied to the drain of nonvolatile memory cell 118 by load line circuit 112 in response to programming power supply voltage VPP and a load line control voltage VLL. VPP is typically 11 to 13 volts, and VLL is two threshold voltage drops less than VPP due to diode connected N-channel transistors 114 and 116. Conventionally, load line circuit 112 includes a transistor that has its gate coupled to VLL and another terminal coupled to VD such that VD is approximately one threshold drop below VLL.
When nonvolatile memory circuit 100 is subjected to changes in process parameters (transistor channel lengths, widths, etc.), changes in operating temperatures, or changes in the programming supply voltage VPP, the load line voltage VLL, and consequently the programming voltage VD, vary. If VD varies too much, nonvolatile memory cell 118 may not be programmed correctly. For example, when process parameters are skewed to a fast process for n-channel transistors 114 and 116, the threshold voltages of these diode connected transistors will drop causing VLL and VD to increase accordingly. Similarly, as the operating temperature of nonvolatile memory circuit 100 increases, the threshold voltages of transistors 114 and 116 will increase causing VLL and VD to drop accordingly. Additionally, if VPP increases during operation of nonvolatile memory circuit 100, VLL and VD will increase accordingly.
When process parameters are skewed to a slow process for n-channel transistors 114 and 116 or if the operating temperature of nonvolatile memory circuit 100 decreases, the threshold voltages of these diode connected transistors will increase causing VLL and VD to drop accordingly. Similarly, if VPP decreases during operation of nonvolatile memory circuit 100, VLL and VD will drop accordingly. If programming voltage VD increases too much, other non-selected cells coupled in parallel with nonvolatile memory cell 118 may experience charge loss from their floating gates towards their drain terminals. This may reduce their margin voltages. Thus, those programmed cells may be erroneously enabled by a smaller than anticipated gate voltage VG. Increasing VD outside the programming window of drain voltages may also cause an undesirable excess amount of charge to be trapped onto the floating gate of nonvolatile memory cell 118. This may cause reliability problems due to the higher electric field placed across the insulating layer separating the floating gate and the channel region of nonvolatile memory cell 118.
FIG. 2 shows another nonvolatile memory circuit 200 that generates a load line voltage VLL from a voltage divider or resistor divider configuration including resistors 202 and 204. VLL is generally less sensitive to process and temperature fluctuations as these variations will generally have the same impact on each of resistor 202 and 204. VLL does, however, vary will changes in the power supply programming voltage VPP such that programming voltage VD will vary with changes in VPP.
Therefore, it is desirable to provide a nonvolatile memory circuit that produces a load line voltage that does not substantially vary with changes in process parameters, operating temperatures, or changes in the power supply voltage applied to the circuit. A stable load line voltage may advantageously produce a programming voltage VD that may be maintained within a programming window in spite of changes in the operating conditions and process variations of the nonvolatile memory circuit.